Field of the Invention
The present invention relates to a delay circuit.
Background Art
FIG. 3 is a circuit diagram illustrating a delay circuit according to a related art.
The related art delay circuit is of an analog type and provides a delay time determined depending on the charging characteristics of a capacitor.
FIG. 4 is a timing chart of the delay circuit according to the related art.
A delay time Td of the delay circuit is expressed by the following equation:Td=Cd×Vref/I1where Cd is a capacitance value of the capacitor, Vref is a reference voltage, and I1 is a charging current. When it is desired to adjust the delay time Td, the capacitor is provided externally and the capacitance value Cd thereof is adjusted.
[Patent Document 1] Japanese Patent Application Laid-Open No. 2003-8410